1. Field of the Invention
The present invention relates to a semiconductor memory and in particular to a static random access memory (SRAM).
2. Description of the Related Art
A SRAM has recently became widespread as a cache memory coupling a central processing unit (CPU) to a dynamic random access memory (DRAM) in order to accelerate data transfer within a system-on-chip. As memory devices continue to shrink in size over time, so do the individual memory cells and hence the individual devices such as transistors within the memory cells. A problem associated with SRAM device miniaturization occurs. Off-state-leakage currents may generate in transfer transistors within the memory cells that are not accessed to read signals: The off-state-leakage currents may cause a wrong signal transmission in the memory devices.
An existing method for dealing with the off-state-leakage currents within the memory cells is to break current paths including the bit lines where leakage currents generate as disclosed in published Japanese Patent Application H11-16367. However, many memory cells are not available by breaking the bit lines generating the leakage currents. Since 256 memory cells are generally connected to a single bit line, a large number of the memory cells are not available when the leakage currents generate in a plurality of bit lines.